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| DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port October 1986 Revised April 2000 DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port General Description These universal, 9-bit parity generators/checkers utilize advanced Schottky high performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word length capability is easily expanded by cascading. The DM74AS286 can be used to upgrade the performance of most systems utilizing the DM74AS280 parity generator/ checker. Although the DM74AS286 is implemented without expander inputs, the corresponding function is provided by the availability of an input pin XMIT. XMIT is a control line which makes parity error output active and parity an input port when HIGH; when LOW, parity error output is inactive and parity becomes an output port. In addition, parity I/O control circuitry contains a feature to keep the I/O port in the 3-STATE during power UP or DOWN to prevent bus glitches. Features s PNP inputs to reduce bus loading s Generates either odd or even parity for nine data lines s Inputs are buffered to lower the drive requirements s Can be used to upgrade existing systems using MSI parity circuits s Cascadable for n-bits s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s A parity I/O portable to drive bus Ordering Code: Order Number DM74AS286M DM74AS286N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Function Table Number of Inputs (A thru I) that are HIGH 0, 2, 4, 6, 8 1, 3, 5, 7, 9 0, 2, 4, 6, 8 0, 2, 4, 6, 8 1, 3, 5, 7, 9 1, 3, 5, 7, 9 L = LOW Logic Level H = HIGH Logic Level N/A = Not Applicable Parity I/O Input Output N/A N/A H L H L H L N/A N/A N/A N/A Parity XMIT Error L L H H H H H H H L L H Mode of Operation Parity Generator Parity Checker Parity Checker (c) 2000 Fairchild Semiconductor Corporation DS006305 www.fairchildsemi.com DM74AS286 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package 77.0C/W 108.0C/W 7V 7V 0C to +70C -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Operating Free-Air Temperature Parity I/O Parity Error Parity I/O Parity Error 0 Parameter Min 4.5 2 0.8 -15 -2 48 20 70 Typ 5 Max 5.5 Units V V V mA mA mA mA C Electrical Characteristics over recommended free-air temperature range. All typical values are measured at VCC = 5V, T A = 25C. Symbol VIK VOH VOL II IIH IIL IO ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current at Maximum Input Voltage HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current Conditions VCC = 4.5V, IIN = -18 mA IOH = Max, VCC = 4.5V VCC = 4.5V to 5.5V, IOH = -2 mA VCC = 4.5V, IOL = Max VCC = 5.5V, VIH = 7V (VI = 5.5V for Parity I/O) VCC = 5.5V VIH = 2.7V (Note 2) VCC = 5.5V, VIL = 0.4V (Note 2) VCC = 5.5V, VOUT = 2.25V VCC = 5.5V, Transmit Mode XMIT = LOW Receive Mode XMIT = HIGH Note 2: For I/O ports, the parameters IIH and IIL include the OFF-state current, IOZH and IOZL. Min 2.4 VCC - 2 Typ 3.2 0.35 Max -1.2 Units V V V 0.5 0.1 V mA A mA mA mA mA Others Parity I/O -30 20 50 -0.5 -112 43 50 www.fairchildsemi.com 2 DM74AS286 Switching Characteristics over recommended supply and temperature range Symbol Parameter tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Time from LOW-to-HIGH Level Output Propagation Delay Time from HIGH-to-LOW Level Output Propagation Delay Time from LOW-to-HIGH Level Output Propagation Delay Time from HIGH-to-LOW Level Output Propagation Delay Time from LOW-to-HIGH Level Output Propagation Delay Time from HIGH-to-LOW Level Output tPZL tPLZ tPZH tPHZ Output Enable Time to LOW Level Output Disable Time from LOW Level Output Disable Time from HIGH Level Output Enable Time to HIGH Level From Any Data Input Any Data Input Any Data Input Any Data Input Parity I/O Parity I/O XMIT XMIT XMIT XMIT To Parity I/O Parity I/O Parity Error Parity Error Parity Error Parity Error Parity I/O Parity I/O Parity I/O Parity I/O Min 3 3 3 3 3 3 3 3 3 3 Max 15 14 16.5 16.5 9 9 16 10 13 11.5 Units ns ns ns ns ns ns ns ns ns ns Typical Applications Number of Inputs that are Logic "1" 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 Even Odd Parity Result Output L H FIGURE 1. Dedicated 10-Bit Parity Sensing Configuration 3 www.fairchildsemi.com DM74AS286 Typical Applications (Continued) Direction Control (XMIT) H L I/O Direction (Parity I/O) Input (Receive) Output (Transmit) Parity Check Result (Parity Error) Level H L H Result True False N/A Parity Select (Input I) Level H L L = LOW Logic Level H = HIGH Logic Level N/A = Not Applicable Format Even Odd FIGURE 2. Bus I/O Parity Implementation www.fairchildsemi.com 4 DM74AS286 Typical Applications (Continued) Note: Parity format in this configuration is "odd parity" FIGURE 3. 90-Bit Parity Generator/Checker Implementation Using Device Expansion Techniques 5 www.fairchildsemi.com DM74AS286 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.com 6 DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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